145 lines
4.2 KiB
C
145 lines
4.2 KiB
C
/*****************************************
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* VulcanOS Kernel *
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* Developed by Marco 'icebit' Cetica *
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* (c) 2019-2021 *
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* Released under GPLv3 *
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* https://github.com/ice-bit/vulcanos *
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*****************************************/
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#ifndef _IDT_H_
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#define _IDT_H_
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#include <stdint.h>
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/*
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* First a bit of theory:
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* Sometimes you want to interrupt the processor from what it is currently doing
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* and force it to do something more "critical", such as a timer update or a keyboard interrupt
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* request(IRQ) fires. The processor, then, will handle those IRQs activating an
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* interrupt handler(ISR, Interrupt Service Routines). In order to know where to find those
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* ISRs, the CPU will use the IDT. So we can say that the Interrupt Description Table
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* is another data structure(organized the same way as the GDT) that will provide a list
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* of interrupts handlers(ISRs) to the CPU.
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*/
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// Reserved bits in IDT entries
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#define IDT_FLAG_RESERVED 0x0E
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// PIC
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#define PIC1 0x20 // I/O address for master PIC
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#define PIC2 0xA0 // I/O address for slave PIC
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#define PIC1_COMMAND PIC1
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#define PIC1_DATA (PIC1+1)
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#define PIC2_COMMAND PIC2
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#define PIC2_DATA (PIC2+1)
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#define PIC1_START_INTERRUPT 0x20 // Master PIC after remapping
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#define PIC2_START_INTERRUPT 0x28 // Slave PIC after remapping
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#define PIC_EOI 0x20 // End of interrupt
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#define ICW1_ICW4 0x01
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#define ICW1_SINGLE 0x02
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#define ICW1_INTERVAL4 0x04
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#define ICW1_LEVEL 0x08
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#define ICW1_INIT 0x10
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#define ICW4_8086 0x01 // 8086/88 (MCS-80/85) mode
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#define ICW4_AUTO 0x02
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#define ICW4_BUF_SLAVE 0x08
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#define ICW4_BUF_MASTER 0x0C
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#define ICW4_SFNM 0x10
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/* Interrupt Descriptor Table */
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/* idt_flags contains access flag of a single IDT entry
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* | 0 - 4 | 5 - 6 | 7 |
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* | res | dpl | p |
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* res: always 0x0E
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* dpl: ring num (0 - 3)
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* p: segment present (bool)
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*/
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struct idt_flags {
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uint8_t reserved: 5;
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uint8_t dpl: 2;
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uint8_t p: 1;
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}__attribute__((packed));
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typedef struct idt_flags idt_flags_t;
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/* idt_entry contains the value of an IDT entry
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* Each entry is 64 bits(like GDT entry)
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* | 0 - 15 | 16 - 31 | 32 - 39 | 40 - 47 | 48 - 63 |
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* | b low | seg sel | res | flags | b high |
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* b low: Lower 16 bits of the base
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* seg sel: Segment selector for code segment
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* res: always 0
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* flags: idt_flags struct
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* b high: Higher 16 bits of the base
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*/
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struct idt_entry {
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uint16_t base_low;
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uint16_t seg_sel;
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uint8_t reserved;
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idt_flags_t flags;
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uint16_t base_high;
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}__attribute__((packed));
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typedef struct idt_entry idt_entry_t;
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/* Also we have to define a pointer to the data structure
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* This is needed to locate it later */
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struct idt_ptr {
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uint16_t limit;
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idt_entry_t *base;
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}__attribute__((packed));
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typedef struct idt_ptr idt_ptr_t;
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/* IDT Kernel API */
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void idt_setup();
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// ISRs method declaration
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extern void isr0();
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extern void isr1();
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extern void isr2();
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extern void isr3();
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extern void isr4();
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extern void isr5();
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extern void isr6();
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extern void isr7();
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extern void isr8();
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extern void isr9();
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extern void isr10();
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extern void isr11();
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extern void isr12();
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extern void isr13();
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extern void isr14();
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extern void isr15();
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extern void isr16();
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extern void isr17();
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extern void isr18();
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extern void isr19();
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extern void isr20();
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extern void isr21();
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extern void isr22();
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extern void isr23();
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extern void isr24();
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extern void isr25();
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extern void isr26();
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extern void isr27();
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extern void isr28();
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extern void isr29();
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extern void isr30();
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extern void isr31();
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extern void irq0();
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extern void irq1();
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extern void irq2();
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extern void irq3();
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extern void irq4();
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extern void irq5();
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extern void irq6();
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extern void irq7();
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extern void irq8();
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extern void irq9();
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extern void irq10();
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extern void irq11();
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extern void irq12();
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extern void irq13();
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extern void irq14();
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extern void irq15();
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#endif
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