73 lines
2.2 KiB
C
73 lines
2.2 KiB
C
/*****************************************
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* VulcanOS Kernel *
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* Developed by Marco 'icebit' Cetica *
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* (c) 2019-2021 *
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* Released under GPLv3 *
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* https://github.com/ice-bit/vulcanos *
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*****************************************/
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#ifndef _ISR_H_
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#define _ISR_H_
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#include <stdint.h>
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/*
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* When we implement ISRs we have to keep in mind that the first 32 interrupts(and so the
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* first 32 ISRs) are reserved by the CPU to signal the kernel about critical actions,
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* such as divide-by-zero or a stack overflow/buffer overflow.
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*
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* Below ther's a list of the first, reserved, interrupts...and yeah, we have to implement
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* all of them by ourself(btw in Assembly) :D
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*
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* 0 - Division by zero exception
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* 1 - Debug exception
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* 2 - Non maskable interrupt
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* 3 - Breakpoint exception
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* 4 - Into detected overflow
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* 5 - Out of bounds exception
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* 6 - Invalid opcode exception
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* 7 - No coprocessor exception
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* 8 - Double fault (pushes an error code)
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* 9 - Coprocessor segment overrun
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* 10 - Bad TSS (pushes an error code)
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* 11 - Segment not present (pushes an error code)
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* 12 - Stack fault (pushes an error code)
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* 13 - General protection fault (pushes an error code)
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* 14 - Page fault (pushes an error code)
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* 15 - Unknown interrupt exception
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* 16 - Coprocessor fault
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* 17 - Alignment check exception
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* 18 - Machine check exception
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* 19-31 - Reserved */
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#define IRQ0 32
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#define IRQ1 33
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#define IRQ2 34
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#define IRQ3 35
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#define IRQ4 36
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#define IRQ5 37
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#define IRQ6 38
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#define IRQ7 39
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#define IRQ8 40
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#define IRQ9 41
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#define IRQ10 42
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#define IRQ11 43
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#define IRQ12 44
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#define IRQ13 45
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#define IRQ14 46
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#define IRQ15 47
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typedef struct registers {
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uint32_t ds; // Data segment
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uint32_t edi, esi, ebp, esp, ebx, edx, ecx, eax; // Pushed with pusha
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uint32_t int_num, err_code; // Interrupt number and error code
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uint32_t eip, cs, eflags, usereap, ss; // Pushed by CPU
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} registers_t;
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typedef void (*isr_t)(registers_t);
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void ack_irq(uint32_t int_num);
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void register_interrupt_handler(uint8_t n, isr_t handler);
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#endif
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