4 Commits

Author	SHA1	Message	Date
Marco Cetica	f263f3f481	Added initrd driver	2021-02-05 13:05:05 +01:00
Marco Cetica	1b207add8c	Refactoring assembly entry point	2021-02-03 15:59:42 +01:00
Cetica Marco	21f017f13c	Added time RTC library	2021-01-02 17:49:15 +01:00
ice-bit	7f737e6f02	Added ordered_list driver and some parts of init ram disk	2019-09-14 12:33:51 +02:00