Refactoring assembly entry point
This commit is contained in:
Marco Cetica
@@ -1,8 +1,9 @@
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OBJS = kernel_loader.asm.o ports.asm.o \
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gdt.asm.o idt.asm.o interrupts.asm.o
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ASM = nasm
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ASMFLAGS = -f elf32
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all: $(OBJS)
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%.asm.o: %.asm
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$(ASM) $(ASMFLAGS) $< -o $@
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OBJS = main.asm.o ports.asm.o \
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gdt.asm.o idt.asm.o \
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interrupts.asm.o header.asm.o
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ASM = nasm
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ASMFLAGS = -f elf32
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all: $(OBJS)
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%.asm.o: %.asm
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$(ASM) $(ASMFLAGS) $< -o $@
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@@ -1,22 +1,22 @@
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; vulcanOS Kernel ;
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; Developed by Marco 'icebit' Cetica ;
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; (c) 2019-2021 ;
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; Released under GPLv3 ;
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; https://github.com/ice-bit/iceOS ;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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global gdt_flush ; for drivers/gdt.c
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section .text
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gdt_flush:
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mov eax, [esp+4] ; get address of gdt_ptr_t
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lgdt [eax] ; Load GDT
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mov ax, 0x10 ; offset in the GDT of the data segment
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mov ds, ax ; Load data segment selectors
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mov es, ax
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mov fs, ax
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mov gs, ax
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mov ss, ax
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jmp 0x08:.flush ; offset in the GDT of the code segment
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.flush:
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ret
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; vulcanOS Kernel ;
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; Developed by Marco 'icebit' Cetica ;
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; (c) 2019-2021 ;
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; Released under GPLv3 ;
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; https://github.com/ice-bit/vulcanos ;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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global gdt_flush ; for drivers/gdt.c
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section .text
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gdt_flush:
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mov eax, [esp+4] ; get address of gdt_ptr_t
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lgdt [eax] ; Load GDT
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mov ax, 0x10 ; offset in the GDT of the data segment
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mov ds, ax ; Load data segment selectors
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mov es, ax
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mov fs, ax
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mov gs, ax
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mov ss, ax
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jmp 0x08:.flush ; offset in the GDT of the code segment
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.flush:
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ret
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19
kernel/cpu/header.asm
Normal file
19
kernel/cpu/header.asm
Normal file
@@ -0,0 +1,19 @@
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; vulcanOS Kernel ;
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; Developed by Marco 'icebit' Cetica ;
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; (c) 2019-2021 ;
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; Released under GPLv3 ;
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; https://github.com/ice-bit/vulcanos ;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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section .multiboot_header
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header_s:
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dd 0xE85250D6 ; Magic number for multiboot
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dd 0 ; Protected mode flag
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dd header_e - header_s ; Header length
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dd 0x100000000 - (0xE85250D6 + 0 + (header_e - header_s)) ; Checksum
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; Other flags
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dw 0 ; Type
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dw 0 ; Flags
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dw 0 ; Size
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header_e:
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@@ -1,14 +1,14 @@
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; vulcanOS Kernel ;
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; Developed by Marco 'icebit' Cetica ;
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; (c) 2019-2021 ;
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; Released under GPLv3 ;
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; https://github.com/ice-bit/iceOS ;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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global idt_flush ; for drivers/idt.c
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section .text
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idt_flush:
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mov eax, [esp+4] ; Retrieve idt_ptr_t*
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lidt [eax]
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ret
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; vulcanOS Kernel ;
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; Developed by Marco 'icebit' Cetica ;
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; (c) 2019-2021 ;
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; Released under GPLv3 ;
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; https://github.com/ice-bit/vulcanos ;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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global idt_flush ; for drivers/idt.c
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section .text
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idt_flush:
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mov eax, [esp+4] ; Retrieve idt_ptr_t*
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lidt [eax]
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ret
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@@ -1,159 +1,159 @@
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; vulcanOS Kernel ;
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; Developed by Marco 'icebit' Cetica ;
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; (c) 2019-2021 ;
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; Released under GPLv3 ;
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; https://github.com/ice-bit/iceOS ;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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extern isr_handler ; Defined in drivers/isr.h
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extern irq_handler ; Defined in drivers/isr.h
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; Let's implement all ISR in a very handy way
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%macro ISR_NOERRCODE 1
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global isr%1
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isr%1:
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cli ; Disable interrupts
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push byte 0 ; Push dummy error code
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push byte %1 ; Push interrupt number
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jmp isr_common ; goto ISR handler
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%endmacro
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%macro ISR_ERRCODE 1
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global isr%1
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isr%1:
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cli ; Disable interrupts
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push byte %1 ; Push interrupt number
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jmp isr_common ; goto ISR handler
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%endmacro
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; Now we have to do the same thing for Interrupt Requests,
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; in this case the first parameter is the IRQ number while
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; the second one is the ISR number to be remapped to
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%macro IRQ 2
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global irq%1
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irq%1:
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cli ; Disable interrupts
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push byte 0 ; Push dummy error code
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push byte %2 ; Push interrupt number
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jmp irq_common ; goto IRQ handler
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%endmacro
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; isr_common is a common handler for all
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; Interrupt Service Routines declared in the system
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; It's main scope is to save current register's states
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; into the stack, call the C high level handler
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; and restore the register's original values from
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; the stack
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isr_common:
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;; Save register's content into the stack ;;
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pusha ; Push edi,esi,ebp,esp,ebx,edx,ecx,eax
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mov ax, ds ; Get 16 bits of eax(e.g ds)
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push eax
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mov ax, 0x10 ; Load the kernel data segment descriptor
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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;; Call C handler ;;
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call isr_handler ; Call C handler
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;; Restore register's content from the stack ;;
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pop eax ; Restore original data segment selector
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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popa ; Pop edi,esi,ebp,esp,ebx,edx,ecx,eax
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add esp, 8 ; Cleans up pushed error code and ISR number
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sti ; Re-enable interrupts
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iret ; Pops 5 things: CS, EIP, EFLAGS, SS and ESp
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; irq_common is a common handler for all
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; Interrupt Requests, it's very similar to the
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; ISR one
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irq_common:
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;; Save register's content into the stack ;;
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pusha ; Push edi,esi,ebp,esp,ebx,edx,ecx,eax
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mov ax, ds ; Get 16 bits of eax(e.g ds)
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push eax
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mov ax, 0x10 ; Load the kernel data segment descriptor
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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;; Call C handler ;;
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call irq_handler ; Call C handler
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;; Restore register's content from the stack ;;
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pop ebx ; Restore original data segment selector
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mov ds, bx
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mov es, bx
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mov fs, bx
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mov gs, bx
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popa ; Pop edi,esi,ebp,esp,ebx,edx,ecx,eax
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add esp, 8 ; Cleans up pushed error code and ISR number
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sti ; Re-enable interrupts
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iret ; Pops 5 things: CS, EIP, EFLAGS, SS and ESp
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; Standard x86 ISRs (only 8,10-14 and 17 requires to push error codes to the stack)
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ISR_NOERRCODE 0
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ISR_NOERRCODE 1
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ISR_NOERRCODE 2
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ISR_NOERRCODE 3
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ISR_NOERRCODE 4
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ISR_NOERRCODE 5
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ISR_NOERRCODE 6
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ISR_NOERRCODE 7
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ISR_ERRCODE 8
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ISR_NOERRCODE 9
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ISR_ERRCODE 10
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ISR_ERRCODE 11
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ISR_ERRCODE 12
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ISR_ERRCODE 13
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ISR_ERRCODE 14
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ISR_NOERRCODE 15
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ISR_NOERRCODE 16
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ISR_NOERRCODE 17
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ISR_NOERRCODE 18
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ISR_NOERRCODE 19
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ISR_NOERRCODE 20
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ISR_NOERRCODE 21
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ISR_NOERRCODE 22
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ISR_NOERRCODE 23
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ISR_NOERRCODE 24
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ISR_NOERRCODE 25
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ISR_NOERRCODE 26
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ISR_NOERRCODE 27
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ISR_NOERRCODE 28
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ISR_NOERRCODE 29
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ISR_NOERRCODE 30
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ISR_NOERRCODE 31
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IRQ 0, 32
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IRQ 1, 33
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IRQ 2, 34
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IRQ 3, 35
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IRQ 4, 36
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IRQ 5, 37
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IRQ 6, 38
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IRQ 7, 39
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IRQ 8, 40
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IRQ 9, 41
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IRQ 10, 42
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IRQ 11, 43
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IRQ 12, 44
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IRQ 13, 45
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IRQ 14, 46
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IRQ 15, 47
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; vulcanOS Kernel ;
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; Developed by Marco 'icebit' Cetica ;
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; (c) 2019-2021 ;
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; Released under GPLv3 ;
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; https://github.com/ice-bit/vulcanos ;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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extern isr_handler ; Defined in drivers/isr.h
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extern irq_handler ; Defined in drivers/isr.h
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; Let's implement all ISR in a very handy way
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%macro ISR_NOERRCODE 1
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global isr%1
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isr%1:
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cli ; Disable interrupts
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push byte 0 ; Push dummy error code
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push byte %1 ; Push interrupt number
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jmp isr_common ; goto ISR handler
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%endmacro
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%macro ISR_ERRCODE 1
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global isr%1
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isr%1:
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cli ; Disable interrupts
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push byte %1 ; Push interrupt number
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jmp isr_common ; goto ISR handler
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%endmacro
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; Now we have to do the same thing for Interrupt Requests,
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; in this case the first parameter is the IRQ number while
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; the second one is the ISR number to be remapped to
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%macro IRQ 2
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global irq%1
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irq%1:
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cli ; Disable interrupts
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push byte 0 ; Push dummy error code
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push byte %2 ; Push interrupt number
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jmp irq_common ; goto IRQ handler
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%endmacro
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; isr_common is a common handler for all
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; Interrupt Service Routines declared in the system
|
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; It's main scope is to save current register's states
|
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; into the stack, call the C high level handler
|
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; and restore the register's original values from
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; the stack
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isr_common:
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;; Save register's content into the stack ;;
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pusha ; Push edi,esi,ebp,esp,ebx,edx,ecx,eax
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mov ax, ds ; Get 16 bits of eax(e.g ds)
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push eax
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mov ax, 0x10 ; Load the kernel data segment descriptor
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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;; Call C handler ;;
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call isr_handler ; Call C handler
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;; Restore register's content from the stack ;;
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pop eax ; Restore original data segment selector
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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popa ; Pop edi,esi,ebp,esp,ebx,edx,ecx,eax
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add esp, 8 ; Cleans up pushed error code and ISR number
|
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sti ; Re-enable interrupts
|
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iret ; Pops 5 things: CS, EIP, EFLAGS, SS and ESp
|
||||
|
||||
|
||||
; irq_common is a common handler for all
|
||||
; Interrupt Requests, it's very similar to the
|
||||
; ISR one
|
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irq_common:
|
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;; Save register's content into the stack ;;
|
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pusha ; Push edi,esi,ebp,esp,ebx,edx,ecx,eax
|
||||
|
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mov ax, ds ; Get 16 bits of eax(e.g ds)
|
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push eax
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mov ax, 0x10 ; Load the kernel data segment descriptor
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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;; Call C handler ;;
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call irq_handler ; Call C handler
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;; Restore register's content from the stack ;;
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pop ebx ; Restore original data segment selector
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mov ds, bx
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mov es, bx
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mov fs, bx
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mov gs, bx
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|
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popa ; Pop edi,esi,ebp,esp,ebx,edx,ecx,eax
|
||||
add esp, 8 ; Cleans up pushed error code and ISR number
|
||||
sti ; Re-enable interrupts
|
||||
iret ; Pops 5 things: CS, EIP, EFLAGS, SS and ESp
|
||||
|
||||
; Standard x86 ISRs (only 8,10-14 and 17 requires to push error codes to the stack)
|
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ISR_NOERRCODE 0
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ISR_NOERRCODE 1
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ISR_NOERRCODE 2
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ISR_NOERRCODE 3
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ISR_NOERRCODE 4
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ISR_NOERRCODE 5
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ISR_NOERRCODE 6
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ISR_NOERRCODE 7
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ISR_ERRCODE 8
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ISR_NOERRCODE 9
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ISR_ERRCODE 10
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ISR_ERRCODE 11
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ISR_ERRCODE 12
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ISR_ERRCODE 13
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ISR_ERRCODE 14
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ISR_NOERRCODE 15
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ISR_NOERRCODE 16
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ISR_NOERRCODE 17
|
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ISR_NOERRCODE 18
|
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ISR_NOERRCODE 19
|
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ISR_NOERRCODE 20
|
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ISR_NOERRCODE 21
|
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ISR_NOERRCODE 22
|
||||
ISR_NOERRCODE 23
|
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ISR_NOERRCODE 24
|
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ISR_NOERRCODE 25
|
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ISR_NOERRCODE 26
|
||||
ISR_NOERRCODE 27
|
||||
ISR_NOERRCODE 28
|
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ISR_NOERRCODE 29
|
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ISR_NOERRCODE 30
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ISR_NOERRCODE 31
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||||
|
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IRQ 0, 32
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||||
IRQ 1, 33
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||||
IRQ 2, 34
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||||
IRQ 3, 35
|
||||
IRQ 4, 36
|
||||
IRQ 5, 37
|
||||
IRQ 6, 38
|
||||
IRQ 7, 39
|
||||
IRQ 8, 40
|
||||
IRQ 9, 41
|
||||
IRQ 10, 42
|
||||
IRQ 11, 43
|
||||
IRQ 12, 44
|
||||
IRQ 13, 45
|
||||
IRQ 14, 46
|
||||
IRQ 15, 47
|
||||
|
||||
@@ -1,43 +0,0 @@
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; vulcanOS Kernel ;
|
||||
; Developed by Marco 'icebit' Cetica ;
|
||||
; (c) 2019-2021 ;
|
||||
; Released under GPLv3 ;
|
||||
; https://github.com/ice-bit/iceOS ;
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
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[BITS 32] ; We should be in protected mode
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section .multiboot
|
||||
|
||||
head_s:
|
||||
dd 0xE85250D6 ; Multiboot header magic number
|
||||
dd 0 ; Protected mode flag
|
||||
dd head_e - head_s ; Header length
|
||||
dd 0x100000000 - (0xE85250D6 + 0 + (head_e - head_s)) ; Checksum of above
|
||||
|
||||
; Other flags
|
||||
dw 0 ; type
|
||||
dw 0 ; flags
|
||||
dd 0 ; size
|
||||
|
||||
head_e:
|
||||
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GLOBAL kernel_loader
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EXTERN kernel_main
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section .text
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||||
kernel_loader:
|
||||
mov esp, kernel_stack + KERNEL_STACK_SZ ; Define stack pointer
|
||||
push eax ; Set multiboot header
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||||
call kernel_main ; Jump into kernel's main function
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.loop:
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jmp .loop ; If the kernel returns, go into an infinite loop.
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; This will prevent the CPU to run non-kernel instructions
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; from the memory
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KERNEL_STACK_SZ equ 4096 ; Stack size(4KiB)
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||||
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section .bss
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align 4
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kernel_stack:
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||||
resb KERNEL_STACK_SZ ; Reserve 4 KiB
|
||||
27
kernel/cpu/main.asm
Normal file
27
kernel/cpu/main.asm
Normal file
@@ -0,0 +1,27 @@
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; vulcanOS Kernel ;
|
||||
; Developed by Marco 'icebit' Cetica ;
|
||||
; (c) 2019-2021 ;
|
||||
; Released under GPLv3 ;
|
||||
; https://github.com/ice-bit/vulcanos ;
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
GLOBAL kernel_loader
|
||||
EXTERN kernel_main
|
||||
[BITS 32] ; Ensure we are in protected mode
|
||||
|
||||
section .text
|
||||
kernel_loader:
|
||||
mov esp, kernel_stack + KERNEL_STACK_SZ ; Define stack pointer
|
||||
push eax ; Set multiboot header register
|
||||
call kernel_main ; Call kernel's main function
|
||||
.loop:
|
||||
jmp .loop ; If the kernel returns, go into an endless loop
|
||||
; This will prevent the CPU to execure any non-kernel
|
||||
; instructions.
|
||||
|
||||
KERNEL_STACK_SZ equ 4096 ; Stack size(4KiB)
|
||||
|
||||
section .bss
|
||||
align 4
|
||||
kernel_stack:
|
||||
resb KERNEL_STACK_SZ ; Reserver 4KiB for kernel's stack
|
||||
@@ -1,21 +1,21 @@
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; vulcanOS Kernel ;
|
||||
; Developed by Marco 'icebit' Cetica ;
|
||||
; (c) 2019-2021 ;
|
||||
; Released under GPLv3 ;
|
||||
; https://github.com/ice-bit/iceOS ;
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
global outb ; Output from port
|
||||
global inb ; Input to port
|
||||
|
||||
outb:
|
||||
mov al, [esp + 8]
|
||||
mov dx, [esp + 4]
|
||||
out dx, al
|
||||
ret
|
||||
|
||||
inb:
|
||||
mov dx, [esp + 4]
|
||||
in al, dx
|
||||
ret
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; vulcanOS Kernel ;
|
||||
; Developed by Marco 'icebit' Cetica ;
|
||||
; (c) 2019-2021 ;
|
||||
; Released under GPLv3 ;
|
||||
; https://github.com/ice-bit/vulcanos ;
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
global outb ; Output from port
|
||||
global inb ; Input to port
|
||||
|
||||
outb:
|
||||
mov al, [esp + 8]
|
||||
mov dx, [esp + 4]
|
||||
out dx, al
|
||||
ret
|
||||
|
||||
inb:
|
||||
mov dx, [esp + 4]
|
||||
in al, dx
|
||||
ret
|
||||
|
||||
Reference in New Issue
Block a user